28.2 Floating point instructions

28.2 Floating point instructions

Explanations:

Operands:

r = register, m = memory, m32 = 32 bit memory operand, etc.

Clock cycles:

The numbers are minimum values. Cache misses, misalignment, denormal operands, and exceptions may increase the clock counts considerably.

Pairability:

+ = pairable with FXCH, np = not pairable with FXCH.

i-ov:

Overlap with integer instructions. i-ov = 4 means that the last four clock cycles can overlap with subsequent integer instructions.

fp-ov:

Overlap with floating point instructions. fp-ov = 2 means that the last two clock cycles can overlap with subsequent floating point instructions. (WAIT is considered a floating point instruction here)

Notes:

m) The value to store is needed one clock cycle in advance.

n) 1 if the overlapping instruction is also an FMUL.

o) Cannot overlap integer multiplication instructions.

p) FDIV takes 19, 33, or 39 clock cycles for 24, 53, and 64 bit precision respectively. FIDIV takes 3 clocks more. The precision is defined by bit 8-9 of the floating point control word.

q) The first 4 clock cycles can overlap with preceding integer instructions. See chapter 26.7.

r) clock counts are typical. Trivial cases may be faster, extreme cases may be slower.

s) may be up to 3 clocks more when output needed for FST, FCHS, or FABS.

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